Apparatus and method for detecting single flip-error in a complementary resistive memory
US9934082B2 · kind B2 · utility
2Cited by
3References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 9, 2016 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Dec 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6502
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described is an apparatus which comprises: a complementary resistive memory bit-cell; a first sense amplifier coupled to the complementary resistive memory bit-cell via access devices; a second sense amplifier coupled to the first sense amplifier and to the complementary resistive memory bit-cell via the access devices, wherein the second sense amplifier is operable to detect an error in the complementary resistive memory bit-cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.