Memory write protection for memory corruption detection architectures
US9934164B2 · kind B2 · utility
1Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | Mar 16, 2017 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Mar 16, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory corruption detection technologies are described. A system on a chip (SoC) may include a memory device and a memory controller. The memory device may store data from an application, wherein the memory device comprises a memory corruption detection (MCD) table. The memory controller may be coupled to the memory device. The memory controller may allocate a contiguous memory block in the memory and write a MCD word into the MCD table. The MCD word may include a write protection indicator that indicates a protection mode of a first portion of the contiguous memory block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.