Patent · US Active

Methods, systems, and computer program product for implementing a layout-driven, multi-fabric schematic design

US9934354B1 · kind B1 · utility

12Cited by

79References

20Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Taranjit Singh Kukal · Delhi, IN
Balvinder Singh · Faridabad, IN
Steven R. Durrill · Campbell, US
Arnold Ginetti · Antibes, FR
Vikrant Khanna · Noida, IN
Abhishek Dabral · Noida, IN
Madhur Sharma · Pune, IN
Nikhil Gupta · New Delhi, IN
Ritabrata Bhattacharya · New Delhi, IN

Key dates

Filing date	Jul 8, 2016
Grant date	Apr 3, 2018
Priority date	—
Expiry date	Jul 8, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F2113/18
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Disclosed are techniques for implementing a layout-driven, multi-fabric schematic design of an electronic design. These techniques identify a multi-fabric layout spanning across multiple design fabrics and layout connectivity information and determine a device map that correlates a first set of devices in the multi-fabric layout with respective parasitic models. The device map can be identified one or more pre-existing device maps or can be constructed anew. A multi-fabric schematic can be generated by using at least the respective parasitic models and the layout connectivity information.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.