DRAM data path sharing via a split local data bus
US9934827B2 · kind B2 · utility
5Cited by
6References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2015 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Mar 2, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is memory device and a memory bank, comprising a global data bus, and a local data bus split into two parts, wherein the local data bus is configurable to direct signals to the global data bus. Provided also is a method in which signals are received in a local data bus that is split into two parts, and the signals are directed from the local data bus to the global data bus. Provided also is a computational device comprised of a processor and the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.