Pulse shaping unit cell and array for symmetric updating
US9934838B1 · kind B1 · utility
12Cited by
4References
25Claims
0Family size
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Key dates
| Filing date | May 10, 2017 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | May 10, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/53
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory unit cell and memory array device are provided. The memory unit cell includes a pulse adjustment circuit for providing an adjusted pulse with symmetric weight updating for a given state update in response to an input pulse and state feedback. The memory unit further includes a synapse element having a memory element with hysteresis for storing one of multiple possible states responsive to the adjusted pulse and for providing the state feedback to the pulse adjustment circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.