Semiconductor heterostructures having reduced dislocation pile-ups and related methods
US9934964B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Apr 11, 2016 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Apr 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.