Power line layout in integrated circuits

US9935052B1 · kind B1 · utility

Assignee

• Altera Corporation · US

Inventors

• Hui Liu · Clyde Hill, US
• Karthik Chandrasekar · Kanchinakote, IN
• Kyung Suk Oh · Cupertino, US
• Kaushik Chanda · Fishkill, US
• Arifur Rahman · San Jose, US

Key dates

• Filing date: Nov 26, 2014
• Grant date: Apr 3, 2018
• Expiry date: Dec 18, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/00014
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Circuitry having power lines with comparable path resistances may include input-output blocks in an integrated circuit (IC) that are coupled to respective sets of bumps on the IC. The circuitry may have a core region and a periphery region. Groups of input-output blocks may be formed in the periphery region. A first set of power lines in the circuitry extends from the core region to the first group of input-output blocks whereas a second set of power lines in the circuitry extends from the core region to the second group of input-output blocks. The first and second sets of power lines are physically separate from each other.