Three layer stack structure
US9935087B2 · kind B2 · utility
16Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2017 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Jan 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Vertically stacked system in package structures are described. In an embodiment, a package includes a first level molding and fan out structure, a third level molding and fan out structure, and a second level molding and fan out structure between the first and third levels. The second level molding and fan out structure includes back-to-back facing die, with a front surface of each die bonded to a redistribution layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.