Substrate design for semiconductor packages and method of forming same
US9935090B2 · kind B2 · utility
12Cited by
81References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2015 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Feb 13, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment device includes a first die, a first molding compound extending along sidewalls of the first die, and one or more first redistribution layers (RDLs) on the first die and the first molding compound. The device further includes a device package comprising a plurality of second dies, wherein the device package is bonded to an opposing surface of the one or more first RDLs as the first die and the first molding compound. A package substrate is bonded to the opposing surface of the one or more first RDLs. The package substrate is electrically connected to the first die and the plurality of second dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.