Reduced resistance source and drain extensions in vertical field effect transistors
US9935195B1 · kind B1 · utility
13Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2017 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Jan 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/015
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices and methods of forming the same include forming semiconductor fins on a semiconductor substrate. A bottom source/drain region is formed in the semiconductor substrate. First charged dielectric spacers are formed on sidewalls of the semiconductor fins. A gate stack is formed over the bottom source/drain region. Second charged dielectric spacers are formed on sidewalls of the fin above the gate stack. The fins are recessed to a height below a top level of the second charged dielectric spacers. A top source/drain region is grown from the recessed fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.