Internal spacers for nanowire transistors and method of fabrication thereof
US9935205B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2016 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Oct 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.