CMOS input buffer with low supply current and voltage down shifting
US9935636B1 · kind B1 · utility
2Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2017 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Mar 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for implementing a CMOS input buffer that consumes very low current even when input levels are less than full swing. An additional optional stage enables conversion to very low voltage swing. The circuit can be manufactured with a standard CMOS processing technology and with high immunity to variation of process parameters. The circuit provides some hysteresis response, enhancing the input voltage margin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.