Apparatus and method for centering clock signal in cumulative data eye of parallel data in clock forwarded links
US9935762B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 19, 2016 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Jul 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus for setting the timing of a triggering edge of a clock signal with respect to received parallel data. The apparatus includes a set of flip-flops including respective data inputs, respective clock inputs, and respective data outputs, wherein the set of flip-flops are configured to generate a set of output data at the data output based on parallel data applied to the respective data inputs in response to a triggering edge of a clock signal applied to the clock inputs; a variable delay element configured to apply a calibrated delay to the clock signal; and a controller configured to generate a control signal for the variable delay element to apply the calibrated delay to the clock signal based on the set of output data generated at the data outputs of the set of flip-flops.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.