Memory error recovery
US9940204B2 · kind B2 · utility
1Cited by
11References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2015 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Nov 6, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An aspect includes memory error recovery in a memory system includes detecting an error condition within a memory chip of the memory system. A chip mark is applied to the memory chip to flag the error condition. An address range of the memory chip associated with the error condition is determined. Data are written from the address range of the memory chip to a cache memory. The chip mark is removed based on determining that all of the data from the address range have been written to the cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.