Methods for reducing congestion region in layout area of IC
US9940422B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2015 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Jul 29, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing congestion regions of an integrated circuit is provided. A placement of the IC is obtained, wherein the placement includes a signal path between a first macro module and a second macro module. The signal path passes through a routing area of the placement for transmitting a specific signal. A congestion region of the routing area is identified. The signal path includes at least one cell or routing path in the congestion region. A cost evaluation is obtained for each candidate position of the routing area by moving the cell or the routing path out of the congestion region. The cell is moved to the candidate position having a minimum cost evaluation among the cost evaluations. The placement and the routing paths are simultaneously updated according to the cell moved to the candidate position having the minimum cost evaluation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.