Accurate statistical timing for boundary gates of hierarchical timing models
US9940431B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2016 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Feb 8, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system to improve performance of a semiconductor chip design includes a hierarchical analysis module that determines a hierarchical arrangement of the semiconductor chip design. The hierarchical arrangement includes a plurality of arcs located at different levels internal to the semiconductor chip design. The different levels include a macro level, a unit level and a core level. The system further includes a timing/load analysis module that determines first timing characteristics of at least one first arc in the macro level based on a first load applied to the at least one first arc. The system further determines second timing characteristics of at least one second arc in at least one of the unit level and the core level based on the first timing characteristics, with a portion of the second timing characteristics determined irrespective of the first load.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.