Pre-layer defect site review using design
US9940704B2 · kind B2 · utility
2Cited by
7References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 16, 2016 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Jun 16, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method to image a layer of a wafer based on a coordinate of a defect in a pre-layer of the wafer are disclosed. A design file for the current layer can be aligned to the wafer using an image of the current layer. A design file for a previous layer can be aligned to the design file for the current layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.