High-speed word line decoder and level-shifter
US9940987B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2016 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Jul 28, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory is provided that includes a row decoder that decodes an address into a plurality of decoded signals for selecting a word line to be asserted from a plurality of word lines. Each word line is driven through a decoder level-shifter that processes the decoded signals. Each decoder level-shifter corresponds to a unique combination of the decoded signals. The row decoder is in a logic power domain such that the decoded signals are asserted to a logic power supply voltage. When a decoder level-shifter's unique combination of decoded signals are asserted by the row decoder, the decoder level-shifter drives the corresponding word line with a memory power supply voltage for a memory power domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.