Leakage-aware activation control of a delayed keeper circuit for a dynamic read operation in a memory bit cell
US9940992B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2016 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Apr 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Leakage-aware activation control of a delayed keeper circuit for a dynamic read operation in a memory bit cell is disclosed. In one aspect, a leakage-aware activation control circuit is provided for a dynamic read circuit configured to perform read operations on a memory bit cell. To prevent or mitigate contention between the delayed keeper circuit and a read port circuit in the dynamic read circuit pulling a dynamic node to opposite voltage levels when a read operation is initiated, the leakage-aware activation control circuit is configured to adaptively control activation timing of the delayed keeper circuit based on a comparison of N-type Field-Effect Transistor (NFET) leakage current to P-type FET (PFET) leakage current. In this manner, the leakage-aware activation control circuit can adaptively adjust the activation timing of the delayed keeper circuit based on the actual relative strengths of NFETs and PFETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.