Two step metallization formation
US9941199B2 · kind B2 · utility
1Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 22, 2017 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | May 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure includes a first conductive line, a dielectric layer over the first conductive line, a diffusion barrier layer in the dielectric layer, and a second conductive line in the dielectric layer. The second conductive line includes a first portion of the diffusion barrier layer. A via is underlying the second conductive line and electrically couples the second conductive line to the first conductive line. The via includes a second portion of the diffusion barrier layer, with the second portion of the diffusion barrier layer having a bottom end higher than a bottom surface of the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.