Three-dimensional non-volatile memory device
US9941291B2 · kind B2 · utility
2Cited by
1References
8Claims
0Family size
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Key dates
| Filing date | Oct 9, 2015 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Dec 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/63
Abstract
A semiconductor device includes at least one first conductive layer stacked on a substrate where a cell region and a contact region are defined; at least one first slit passing through the first conductive layer, second conductive layers stacked on the first conductive layer; a second slit passing through the first and second conductive layers and connected with one side of the first slit, and a third slit passing through the first and second conductive layers and connected with the other side of the first slit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.