Fabricating large area multi-tier nanostructures

US9941389B2 · kind B2 · utility

Assignee

• The Board of Regents of the University of Texas System · US

Inventors

• Sidlgata V. Sreenivasan · Austin, US
• Praveen Joseph · White Plains, US
• Ovadia Abed · Austin, US
• Michelle Grigas · Austin, US
• Akhila Mallavarapu · Austin, US
• Paras Ajay · Austin, US

Key dates

• Filing date: Apr 19, 2016
• Grant date: Apr 10, 2018
• Expiry date: Jun 28, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0212
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a single lithography step whereby the need for alignment and overlay in the process is completely eliminated thereby enabling near-zero overlay error. Furthermore, techniques are developed to use these methods to fabricate self-aligned nanoscale multi-level/multi-height patterns with various shapes for master templates, replica templates and nanoimprint based pattern replication. Furthermore, the templates can be used to pattern multiple levels in a sacrificial polymer resist and achieve pattern transfer of the levels into a variety of substrates to form completed large area nanoelectronic and nanophotonic devices using only one patterning step.