MOS transistor and method of manufacturing the same
US9941416B2 · kind B2 · utility
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1References
14Claims
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Assignee
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Key dates
| Filing date | Nov 18, 2016 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Nov 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/514
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MOS transistor includes a semiconductor layer resting on an insulator and having a substantially planar upper surface. The semiconductor layer extends down to a first depth in the channel region, and down to a second depth, greater than the first depth, in the source and drain regions. In the channel region, the semiconductor layer is formed from a portion of an upper semiconductor layer of a silicon on insulator substrate. In the source and drain regions, the semiconductor layer is formed by epitaxially grown semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.