Apparatus and method for latching data including AND-NOR or OR-NAND gate and feedback paths
US9941881B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2017 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Mar 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A latch circuit includes an AND-NOR gate, a NAND gate, and a NOR gate. The AND-NOR gate includes a first AND-input configured to receive input data and a second AND-input coupled to an output of the NAND gate. The AND-NOR gate includes a NOR-input coupled to an output of the NOR gate, and an output configured to generate output data. The NAND gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a clock signal. The NOR gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a complementary clock signal. During a first half clock cycle, the AND-NOR gate passes the data from the input to the output. During a second half clock cycle, the feedback configuration of the AND-NOR gate and the NOR gate latches the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.