Joint rewriting and error correction in write-once memories
US9946475B2 · kind B2 · utility
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25Claims
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Key dates
| Filing date | Jul 5, 2013 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Nov 21, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Both rewriting and error correction are technologies usable for non-volatile memories, such as flash memories. A coding scheme is disclosed herein that combines rewriting and error correction for the write-once memory model. In some embodiments, code construction is based on polar codes, and supports any number of rewrites and corrects a substantial number of errors. The code may be analyzed for a binary symmetric channel. The results can be extended to multi-level cells and more general noise models.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.