Controlling persistent writes to non-volatile memory based on persist buffer data and a persist barrier within a sequence of program instructions

US9946492B2 · kind B2 · utility

Assignees

• Arm Limited · GB
• THE REGENTS OF THE UNIVERSITY OF MICHIGAN · US

Inventors

• Stephan Diestelhorst · Dresden, DE
• Aasheesh Kolli · Palo Alto, US
• Ali Ghassan Saidi · Austin, US
• Peter M. Chen · Ann Arbor, US
• Thomas Friedrich Wenisch · Ann Arbor, US

Key dates

• Filing date: Oct 30, 2015
• Grant date: Apr 17, 2018
• Expiry date: Jan 4, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F12/0246
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A data processing system 2 including non-volatile memory 22 manages the ordering of writes to the non-volatile memory and persist barrier instructions using a persist buffer storing persist buffer data. A write controller responds to the persist buffer data to prevent writing to the non-volatile memory for instructions following a given persist barrier instruction within a sequence of program instructions before the writes to the non-volatile memory which precede that given persist barrier instruction have at least been acknowledged as received by the memory system containing the non-volatile memory. In the case of a multi-core system, cache snooping mechanisms are used to pass persistency dependence data between cores such that strong persist atomicity may be tracked and managed between the cores.