Dynamic control of design clock generation in emulation
US9946823B2 · kind B2 · utility
1Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2013 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Oct 11, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the invention relate to techniques for dynamic control of design clock generation in emulation. A circuit design for verification is analyzed to determine one or more clock-enabling functions for a specific clock signal. Logic for generating a clock status signal based on the one or more clock-enabling signals is then determined. The clock status signal is employed to control clock generation in an emulation system for emulating the circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.