Vertical bit vector shift in memory
US9947376B2 · kind B2 · utility
2Cited by
164References
20Claims
0Family size
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Key dates
| Filing date | Jun 16, 2017 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Jun 16, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples of the present disclosure provide apparatuses and methods for vertical bit vector shift in a memory. An example method comprises storing a vertical bit vector of data in a memory array, wherein the vertical bit vector is stored in memory cells coupled to a sense line and a plurality of access lines and the vertical bit vector is separated by at least one sense line from a neighboring vertical bit vector; and performing, using sensing circuitry, a vertical bit vector shift of a number of elements of the vertical bit vector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.