Techniques for programming of select gates in NAND memory
US9947407B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2017 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | May 19, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.