Apparatus and method for implementing design for testability (DFT) for bitline drivers of memory circuits
US9947419B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2017 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Mar 28, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first bitline driver includes a multiplexer for outputting data and write mask signals in functional mode, and test vector signal in test mode; a latch to latch the data signal in functional mode and the test vector signal in test mode; a latch to latch the write mask signal in functional mode and the test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell based on the data signal. A second bitline driver includes a latch to latch a data signal in functional mode if a write mask signal is deasserted and to latch a test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.