Integrated circuit with a sidewall layer and an ultra-thick metal layer and method of making
US9947577B2 · kind B2 · utility
0Cited by
9References
20Claims
0Family size
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Key dates
| Filing date | Nov 18, 2016 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Nov 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit that includes providing a substrate, a metal layer over the substrate, and a first dielectric layer over the metal layer. The first dielectric layer includes a via. A sidewall layer that includes a silicon compound is in the via. A second dielectric layer is over the sidewall layer and an ultra-thick metal (UTM) layer is in the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.