Semiconductor package assembly with through silicon via interconnect
US9947624B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2016 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Dec 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06544
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor package mounted on a base, having: a semiconductor die, a semiconductor substrate, and a first array of TSV interconnects and a second array of TSV interconnects formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. The assembly further includes a second semiconductor die mounted on the first semiconductor package, having a ground pad thereon. One of the TSV interconnects of the first semiconductor package has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.