Manufacturing method of dual gate oxide semiconductor TFT substrate and substrate thereof
US9947699B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2017 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Jul 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1213
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a dual gate oxide semiconductor TFT substrate utilizes a halftone mask to implement a photo process, which not only accomplishes patterning to an oxide semiconductor layer but also obtains an oxide conductor layer with ion doping. The method implements patterning to a bottom gate isolation layer and a top gate isolation layer at the same time with one photolithographic process. The method implements patterning to second and third metal layers at the same time to obtain a first source, a first drain, a second source, a second drain, a first top gate and a second top gate with one photolithographic process. The method implements patterning to a second flat layer, a passivation layer and a top gate isolation layer at the same time with one photolithographic process. The number of photolithographic processes involved is reduced to nine so as to simplify the manufacturing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.