Chip package and manufacturing method thereof
US9947716B2 · kind B2 · utility
1Cited by
1References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2016 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Nov 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/811
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 μm to 750 μm, and the wall surface of the dam element surrounding the sensing area is a rough surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.