MOS devices with mask layers and methods for forming the same
US9947762B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2015 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Sep 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.