Self-limited inner spacer formation for gate-all-around field effect transistors
US9947767B1 · kind B1 · utility
5Cited by
2References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2017 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Jan 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor devices and methods of forming the same include forming a layer of activating material on sidewalls of a stack of alternating layers of channel material and sacrificial material. The layer of activating material is annealed to cause the activating material to react with the sacrificial material and to form insulating spacers at ends of the layers of sacrificial material. The layer of activating material is etched away to expose ends of the layers of channel material. Source/drain regions are formed on the ends of the layers of channel material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.