Method for forming spacers for a transistor gate
US9947768B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 17, 2016 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Jun 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming spacers of a gate of a field-effect transistor is provided, the gate being located above a layer of a semiconductor material, the method including forming a dielectric layer covering the gate of the transistor; modifying the dielectric layer by putting the dielectric layer into presence with a plasma formed from a gas formed from at least one first non-carbonated gaseous component of which dissociation generates light ions and a second gaseous component comprising at least one species favoring dissociation of the first component in order to form the light ions, wherein a gas ratio between the first component and the second component is between 1:19 and 19:1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.