Semiconductor device
US9948090B2 · kind B2 · utility
1Cited by
1References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2015 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Oct 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/819
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. A gate width of the second transistor is narrower than a gate width of the first transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.