Semiconductor device
US9948283B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 30, 2017 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Jan 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
When a signal of high amplitude is outputted, a drain-to-source voltage exceeding a withstand voltage may be applied. The semiconductor device according to the present invention includes a level shift circuit that outputs a high amplitude signal from the input of a low amplitude logical signal. The level shift circuit includes a series coupling circuit, a first gate control circuit coupled to a first power supply, a second gate control circuit coupled to a second power supply of a potential higher than the potential of the first power supply, and a potential conversion circuit arranged between the first gate control circuit and the series coupling circuit. The potential conversion circuit supplies a first level potential, which is lower than the potential of the first power supply and higher than the potential of the reference power supply, to a gate of an N-channel MOS transistor of the series coupling circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.