Apparatuses and methods for partial bit de-emphasis
US9948300B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 20, 2017 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Mar 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0286
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period proceeding the first portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.