Parallel scheduling of write commands to multiple memory devices
US9952779B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2016 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Jul 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0688
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a link. The processor is configured to select at least first and second memory devices for writing, and to write at least first and second data units in sequence to the first memory device over the link, while avoiding writing to any of the other memory devices until transferal of the at least first and second data units over the link has been completed, to write at least one data unit to the second memory device after transferring the at least first and second data units to the first memory device, and, in response to verifying that the first memory device is ready to receive subsequent data, to write to the first memory device at least a third data unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.