Design/technology co-optimization platform for high-mobility channels CMOS technology
US9953125B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2016 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Jun 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention may provide the capability to design SRAM cells may be designed that is compatible with the requirements of InGaAs integration by selective epitaxy in SiO2 cavities without sacrificing density and area scaling. In an embodiment of the present invention, a computer-implemented method for designing a hybrid integrated circuit may comprise receiving data representing a layout of a static random-access memory cell array, identifying areas between active channel regions that do not overlap with transistor gates of static random-access memory cells of the static random-access memory cell array, selecting from among the identified areas at least one area, expanding the selected areas to determine whether the expanded area intersects with a p-doped active Si semiconductor or p-channel semiconductor area, and marking as Si seed locations the identified expanded areas that do not intersect on both sides with a channel active transistor region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.