Memory controller-controlled refresh abort
US9953694B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2016 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Jun 28, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/0009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory subsystem enables a refresh abort command. A memory controller can issue an abort for an in-process refresh command sent to a memory device. The refresh abort enables the memory controller to more precisely control the timing of operations executed by memory devices in the case where a refresh command causes refresh of multiple rows of memory. The memory controller can issue a refresh command during active operation of the memory device, which is active operation refresh as opposed to self-refresh when the memory device controls refreshing. The memory controller can then issue a refresh abort during the refresh, and prior to completion of the refresh. The memory controller thus has deterministic control over both the start of refresh as well as when the memory device can be made available for access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.