Planar memory cell architectures in resistive memory devices
US9953705B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 26, 2016 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Apr 26, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/75
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive random access memory (ReRAM) array is provided. The ReRAM array includes a plurality of memory cells each comprising resistive memory material formed into a layer of a substrate, with resistance properties of the resistive memory material corresponding to data bits stored by the memory cells. The ReRAM array also includes a plurality of interconnect features each comprising conductive material between adjacent memory cells formed into the layer of the substrate, and gate portions coupled onto the memory cells and configured to individually alter the resistance properties of the resistive memory material of associated memory cells responsive to at least voltages applied to the gate portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.