Flash memory cell and associated decoders
US9953719B2 · kind B2 · utility
3Cited by
1References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 18, 2016 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | May 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6892
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.