Structure and method to improve FAV RIE process margin and electromigration
US9953865B1 · kind B1 · utility
20Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2016 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Oct 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76883
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming fully aligned vias in a semiconductor device includes forming an Mx level interconnect line embedded in an Mx interlevel dielectric (ILD). The Mx level interconnect is recessed below the Mx interlevel dielectric or a dielectric is selectively deposited on the Mx interlevel dielectric. The method also includes laterally etching the exposed upper portion of the Mx interlevel dielectric bounding the recess or laterally etching the selectively deposited dielectric. A dielectric cap layer and an Mx+1 level interlevel dielectric is deposited on top of the Mx interlevel dielectric, and a via opening is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.