Patent · US Active

Process for fabricating semiconductor nanowires or microwires having insulated roots

US9954141B2 · kind B2 · utility

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Key dates

Filing dateDec 24, 2015
Grant dateApr 24, 2018
Priority date
Expiry dateDec 24, 2035

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY02P70/50

Abstract

A process for fabricating an electronic device including a substrate and microwires or nanowires resting on the substrate, the process including successive steps of covering the wires with an insulating layer, covering the insulating layer with an opaque layer, depositing a first photoresist layer over the substrate between the wires, etching the first photoresist layer over a first thickness by photolithography, etching the first photoresist layer remaining after the preceding step over a second thickness by plasma etching, etching the portion of the opaque layer not covered by the first photoresist layer remaining after the preceding step, etching the portion of the insulating layer not covered by the opaque layer, removing the first photoresist layer remaining after the preceding step, and removing the opaque layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.