Shared row buffer system for asymmetric memory
US9959205B2 · kind B2 · utility
1Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | May 13, 2015 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | Jul 16, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture for improved memory access in asymmetric memories provides a set of shared row buffers that may be freely allocated between slow and fast memory banks of the asymmetric memory. This permits allocation of row buffers dynamically between the slow and fast memory banks to improve execution speeds and also permits a lightweight memory swap procedure for moving data between the slow and fast memory banks with low processor and memory channel overheads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.