Supporting configurable security levels for memory address ranges
US9959418B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2015 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | Oct 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2113
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor implementing techniques for supporting configurable security levels for memory address ranges is disclosed. In one embodiment, the processor includes a processing core a memory controller, operatively coupled to the processing core, to access data in an off-chip memory and a memory encryption engine (MEE) operatively coupled to the memory controller. The MEE is to responsive to detecting a memory access operation with respect to a memory location identified by a memory address within a memory address range associated with the off-chip memory, identify a security level indicator associated with the memory location based on a value stored on a security range register. The MEE is further to access at least a portion of a data item associated with the memory address range of the off-chip memory in view of the security level indicator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.