Memory array and method of forming the same
US9959911B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2017 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | Feb 27, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array includes a first column of memory cells, a second column of memory cells and a set of switching elements. The first column of memory cells includes a first bit line, a first word line and a second bit line. The second column of memory cells includes the second bit line, a second word line and a third bit line. The first and second column of memory cells are configured to share the second bit line. The first and second bit lines are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane. An amount of bit line switching elements in the set of bit line switching elements is equal to N*2, where N is an amount of columns of memory cells in the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.